This invention relates to a semiconductor memory device having a redundant fuse circuit, and particularly to a redundant fuse circuit having a fuse broken by an electric current, capable of contributing to a yield-enhancement of a dynamic random access memory (hereinafter called "DRAM").
Since a conventional DRAM is hard to obtain a chip operated on an all-bit basis, an operated memory bit (memory cell) has been confirmed once by a memory tester (hereinafter called "first probing test"). Thereafter, a decision (hereinafter called "redundant retrieval") as to whether a failure-detected bit can be replaced by a prepared redundant bit (hereinafter called "redundant bit"), is made When it is found that the failure-detected bit can be replaced by the prepared redundant bit, data (hereinafter called "redundant data") for its replacement is outputted. A prepared fuse (hereinafter called "redundant fuse"), which allows the logical replacement of the defective bit with the redundant bit by its cutting, is cut (hereinafter fused-cut) by a laser repair device based on the redundant data. Thus, the defective bit is replaced with the redundant bit and a test (hereinafter called "second probing test") to determine whether the replaced chip is good or not is performed again by the memory tester, whereby a DRAM determined as a good product is obtained.
As Japanese Patent Publications each disclosing such a redundant fuse, may be mentioned Japanese Patent Application Laid-Open Nos. Hei 4-14700, 5-74190, 6-195995, 7-169293, etc.
Since, however, the first and second probing tests employed in the conventional DRAM make use of the memory tester and the fuse cut is performed using a device different from the laser repair device, the sample must be shifted in the respective processes for the tests, so that much time was required till the completion of all the tests.